Gate arrays are extremely complex integrated circuits, which are usually designed using a computerized design system comprised of a computer and the appropriate software. The design is typically divided into functional blocks made up of logic cells, which operate together to execute the desired function. A design may simulate correctly before layout but due to signal delays caused by the physical implementation it may not work when produced. Part of the physical implementation that can affect signal delay times is the logic cell placement process.
The placement process (floorplanning) has traditionally been a non-user interactive procedure with very little pre-placement control. All of the logic components are placed automatically following some basic algorithm for "optimal" placement. This approach, however, does not consider design specific information such as correspondence between logic cells and functional blocks and interaction between functional blocks. This means that functional blocks can end up mixed and spread throughout all over the design area with no regard for intended interaction and critical timing. The latest generation of placement software products can handle directive parameters that enhance placement but lack an operational interface to process hierarchical design information under control of a user.
In view of the above, it would be desirable to provide a user-controlled placement system (floorplanner), which creates placement directives for the hierarchical groups of the logic cells on an integrated circuit.